winhvplatformdefs.h 54 KB

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  1. /**
  2. * This file is part of the mingw-w64 runtime package.
  3. * No warranty is given; refer to the file DISCLAIMER within this package.
  4. */
  5. #ifndef _WINHVAPIDEFS_H_
  6. #define _WINHVAPIDEFS_H_
  7. typedef enum WHV_CAPABILITY_CODE {
  8. WHvCapabilityCodeHypervisorPresent = 0x00000000,
  9. WHvCapabilityCodeFeatures = 0x00000001,
  10. WHvCapabilityCodeExtendedVmExits = 0x00000002,
  11. WHvCapabilityCodeExceptionExitBitmap = 0x00000003,
  12. WHvCapabilityCodeX64MsrExitBitmap = 0x00000004,
  13. WHvCapabilityCodeGpaRangePopulateFlags = 0x00000005,
  14. WHvCapabilityCodeSchedulerFeatures = 0x00000006,
  15. WHvCapabilityCodeProcessorVendor = 0x00001000,
  16. WHvCapabilityCodeProcessorFeatures = 0x00001001,
  17. WHvCapabilityCodeProcessorClFlushSize = 0x00001002,
  18. WHvCapabilityCodeProcessorXsaveFeatures = 0x00001003,
  19. WHvCapabilityCodeProcessorClockFrequency = 0x00001004,
  20. WHvCapabilityCodeInterruptClockFrequency = 0x00001005,
  21. WHvCapabilityCodeProcessorFeaturesBanks = 0x00001006,
  22. WHvCapabilityCodeProcessorFrequencyCap = 0x00001007,
  23. WHvCapabilityCodeSyntheticProcessorFeaturesBanks = 0x00001008,
  24. WHvCapabilityCodeProcessorPerfmonFeatures = 0x00001009
  25. } WHV_CAPABILITY_CODE;
  26. typedef union WHV_CAPABILITY_FEATURES {
  27. __C89_NAMELESS struct {
  28. UINT64 PartialUnmap : 1;
  29. UINT64 LocalApicEmulation : 1;
  30. UINT64 Xsave : 1;
  31. UINT64 DirtyPageTracking : 1;
  32. UINT64 SpeculationControl : 1;
  33. UINT64 ApicRemoteRead : 1;
  34. UINT64 IdleSuspend : 1;
  35. UINT64 VirtualPciDeviceSupport : 1;
  36. UINT64 IommuSupport : 1;
  37. UINT64 VpHotAddRemove : 1;
  38. UINT64 Reserved : 54;
  39. };
  40. UINT64 AsUINT64;
  41. } WHV_CAPABILITY_FEATURES;
  42. C_ASSERT(sizeof(WHV_CAPABILITY_FEATURES) == sizeof(UINT64));
  43. typedef union WHV_EXTENDED_VM_EXITS {
  44. __C89_NAMELESS struct {
  45. UINT64 X64CpuidExit : 1;
  46. UINT64 X64MsrExit : 1;
  47. UINT64 ExceptionExit : 1;
  48. UINT64 X64RdtscExit : 1;
  49. UINT64 X64ApicSmiExitTrap : 1;
  50. UINT64 HypercallExit : 1;
  51. UINT64 X64ApicInitSipiExitTrap : 1;
  52. UINT64 X64ApicWriteLint0ExitTrap : 1;
  53. UINT64 X64ApicWriteLint1ExitTrap : 1;
  54. UINT64 X64ApicWriteSvrExitTrap : 1;
  55. UINT64 UnknownSynicConnection : 1;
  56. UINT64 RetargetUnknownVpciDevice : 1;
  57. UINT64 X64ApicWriteLdrExitTrap : 1;
  58. UINT64 X64ApicWriteDfrExitTrap : 1;
  59. UINT64 GpaAccessFaultExit : 1;
  60. UINT64 Reserved : 49;
  61. };
  62. UINT64 AsUINT64;
  63. } WHV_EXTENDED_VM_EXITS;
  64. C_ASSERT(sizeof(WHV_EXTENDED_VM_EXITS) == sizeof(UINT64));
  65. typedef enum WHV_PROCESSOR_VENDOR {
  66. WHvProcessorVendorAmd = 0x0000,
  67. WHvProcessorVendorIntel = 0x0001,
  68. WHvProcessorVendorHygon = 0x0002
  69. } WHV_PROCESSOR_VENDOR;
  70. typedef union WHV_PROCESSOR_FEATURES {
  71. __C89_NAMELESS struct {
  72. UINT64 Sse3Support : 1;
  73. UINT64 LahfSahfSupport : 1;
  74. UINT64 Ssse3Support : 1;
  75. UINT64 Sse4_1Support : 1;
  76. UINT64 Sse4_2Support : 1;
  77. UINT64 Sse4aSupport : 1;
  78. UINT64 XopSupport : 1;
  79. UINT64 PopCntSupport : 1;
  80. UINT64 Cmpxchg16bSupport : 1;
  81. UINT64 Altmovcr8Support : 1;
  82. UINT64 LzcntSupport : 1;
  83. UINT64 MisAlignSseSupport : 1;
  84. UINT64 MmxExtSupport : 1;
  85. UINT64 Amd3DNowSupport : 1;
  86. UINT64 ExtendedAmd3DNowSupport : 1;
  87. UINT64 Page1GbSupport : 1;
  88. UINT64 AesSupport : 1;
  89. UINT64 PclmulqdqSupport : 1;
  90. UINT64 PcidSupport : 1;
  91. UINT64 Fma4Support : 1;
  92. UINT64 F16CSupport : 1;
  93. UINT64 RdRandSupport : 1;
  94. UINT64 RdWrFsGsSupport : 1;
  95. UINT64 SmepSupport : 1;
  96. UINT64 EnhancedFastStringSupport : 1;
  97. UINT64 Bmi1Support : 1;
  98. UINT64 Bmi2Support : 1;
  99. UINT64 Reserved1 : 2;
  100. UINT64 MovbeSupport : 1;
  101. UINT64 Npiep1Support : 1;
  102. UINT64 DepX87FPUSaveSupport : 1;
  103. UINT64 RdSeedSupport : 1;
  104. UINT64 AdxSupport : 1;
  105. UINT64 IntelPrefetchSupport : 1;
  106. UINT64 SmapSupport : 1;
  107. UINT64 HleSupport : 1;
  108. UINT64 RtmSupport : 1;
  109. UINT64 RdtscpSupport : 1;
  110. UINT64 ClflushoptSupport : 1;
  111. UINT64 ClwbSupport : 1;
  112. UINT64 ShaSupport : 1;
  113. UINT64 X87PointersSavedSupport : 1;
  114. UINT64 InvpcidSupport : 1;
  115. UINT64 IbrsSupport : 1;
  116. UINT64 StibpSupport : 1;
  117. UINT64 IbpbSupport : 1;
  118. UINT64 Reserved2 : 1;
  119. UINT64 SsbdSupport : 1;
  120. UINT64 FastShortRepMovSupport : 1;
  121. UINT64 Reserved3 : 1;
  122. UINT64 RdclNo : 1;
  123. UINT64 IbrsAllSupport : 1;
  124. UINT64 Reserved4 : 1;
  125. UINT64 SsbNo : 1;
  126. UINT64 RsbANo : 1;
  127. UINT64 Reserved5 : 1;
  128. UINT64 RdPidSupport : 1;
  129. UINT64 UmipSupport : 1;
  130. UINT64 MdsNoSupport : 1;
  131. UINT64 MdClearSupport : 1;
  132. UINT64 TaaNoSupport : 1;
  133. UINT64 TsxCtrlSupport : 1;
  134. UINT64 Reserved6 : 1;
  135. };
  136. UINT64 AsUINT64;
  137. } WHV_PROCESSOR_FEATURES;
  138. C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES) == sizeof(UINT64));
  139. typedef union WHV_PROCESSOR_FEATURES1 {
  140. __C89_NAMELESS struct {
  141. UINT64 ACountMCountSupport : 1;
  142. UINT64 TscInvariantSupport : 1;
  143. UINT64 ClZeroSupport : 1;
  144. UINT64 RdpruSupport : 1;
  145. UINT64 Reserved2 : 2;
  146. UINT64 NestedVirtSupport : 1;
  147. UINT64 PsfdSupport: 1;
  148. UINT64 CetSsSupport : 1;
  149. UINT64 CetIbtSupport : 1;
  150. UINT64 VmxExceptionInjectSupport : 1;
  151. UINT64 Reserved4 : 1;
  152. UINT64 UmwaitTpauseSupport : 1;
  153. UINT64 MovdiriSupport : 1;
  154. UINT64 Movdir64bSupport : 1;
  155. UINT64 CldemoteSupport : 1;
  156. UINT64 SerializeSupport : 1;
  157. UINT64 TscDeadlineTmrSupport : 1;
  158. UINT64 TscAdjustSupport : 1;
  159. UINT64 FZLRepMovsb : 1;
  160. UINT64 FSRepStosb : 1;
  161. UINT64 FSRepCmpsb : 1;
  162. UINT64 TsxLdTrkSupport : 1;
  163. UINT64 Reserved5 : 41;
  164. };
  165. UINT64 AsUINT64;
  166. } WHV_PROCESSOR_FEATURES1;
  167. C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES1) == sizeof(UINT64));
  168. #define WHV_PROCESSOR_FEATURES_BANKS_COUNT 2
  169. typedef struct WHV_PROCESSOR_FEATURES_BANKS {
  170. UINT32 BanksCount;
  171. UINT32 Reserved0;
  172. __C89_NAMELESS union {
  173. __C89_NAMELESS struct {
  174. WHV_PROCESSOR_FEATURES Bank0;
  175. WHV_PROCESSOR_FEATURES1 Bank1;
  176. };
  177. UINT64 AsUINT64[WHV_PROCESSOR_FEATURES_BANKS_COUNT];
  178. };
  179. } WHV_PROCESSOR_FEATURES_BANKS;
  180. C_ASSERT(sizeof(WHV_PROCESSOR_FEATURES_BANKS) == sizeof(UINT64) * (WHV_PROCESSOR_FEATURES_BANKS_COUNT + 1));
  181. typedef union WHV_SYNTHETIC_PROCESSOR_FEATURES {
  182. __C89_NAMELESS struct {
  183. UINT64 HypervisorPresent:1;
  184. UINT64 Hv1:1;
  185. UINT64 AccessVpRunTimeReg:1;
  186. UINT64 AccessPartitionReferenceCounter:1;
  187. UINT64 AccessSynicRegs:1;
  188. UINT64 AccessSyntheticTimerRegs:1;
  189. #ifdef __x86_64__
  190. UINT64 AccessIntrCtrlRegs:1;
  191. #else
  192. UINT64 ReservedZ6:1;
  193. #endif
  194. UINT64 AccessHypercallRegs:1;
  195. UINT64 AccessVpIndex:1;
  196. UINT64 AccessPartitionReferenceTsc:1;
  197. #ifdef __x86_64__
  198. UINT64 AccessGuestIdleReg:1;
  199. UINT64 AccessFrequencyRegs:1;
  200. #else
  201. UINT64 ReservedZ10:1;
  202. UINT64 ReservedZ11:1;
  203. #endif
  204. UINT64 ReservedZ12:1;
  205. UINT64 ReservedZ13:1;
  206. UINT64 ReservedZ14:1;
  207. #ifdef __x86_64__
  208. UINT64 EnableExtendedGvaRangesForFlushVirtualAddressList:1;
  209. #else
  210. UINT64 ReservedZ15:1;
  211. #endif
  212. UINT64 ReservedZ16:1;
  213. UINT64 ReservedZ17:1;
  214. UINT64 FastHypercallOutput:1;
  215. UINT64 ReservedZ19:1;
  216. UINT64 ReservedZ20:1;
  217. UINT64 ReservedZ21:1;
  218. UINT64 DirectSyntheticTimers:1;
  219. UINT64 ReservedZ23:1;
  220. UINT64 ExtendedProcessorMasks:1;
  221. #ifdef __x86_64__
  222. UINT64 TbFlushHypercalls:1;
  223. #else
  224. UINT64 ReservedZ25:1;
  225. #endif
  226. UINT64 SyntheticClusterIpi:1;
  227. UINT64 NotifyLongSpinWait:1;
  228. UINT64 QueryNumaDistance:1;
  229. UINT64 SignalEvents:1;
  230. UINT64 RetargetDeviceInterrupt:1;
  231. UINT64 Reserved:33;
  232. };
  233. UINT64 AsUINT64;
  234. } WHV_SYNTHETIC_PROCESSOR_FEATURES;
  235. C_ASSERT(sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES) == 8);
  236. #define WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS_COUNT 1
  237. typedef struct WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS {
  238. UINT32 BanksCount;
  239. UINT32 Reserved0;
  240. __C89_NAMELESS union {
  241. __C89_NAMELESS struct {
  242. WHV_SYNTHETIC_PROCESSOR_FEATURES Bank0;
  243. };
  244. UINT64 AsUINT64[WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS_COUNT];
  245. };
  246. } WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS;
  247. C_ASSERT(sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS) == 16);
  248. typedef union _WHV_PROCESSOR_XSAVE_FEATURES {
  249. __C89_NAMELESS struct {
  250. UINT64 XsaveSupport : 1;
  251. UINT64 XsaveoptSupport : 1;
  252. UINT64 AvxSupport : 1;
  253. UINT64 Avx2Support : 1;
  254. UINT64 FmaSupport : 1;
  255. UINT64 MpxSupport : 1;
  256. UINT64 Avx512Support : 1;
  257. UINT64 Avx512DQSupport : 1;
  258. UINT64 Avx512CDSupport : 1;
  259. UINT64 Avx512BWSupport : 1;
  260. UINT64 Avx512VLSupport : 1;
  261. UINT64 XsaveCompSupport : 1;
  262. UINT64 XsaveSupervisorSupport : 1;
  263. UINT64 Xcr1Support : 1;
  264. UINT64 Avx512BitalgSupport : 1;
  265. UINT64 Avx512IfmaSupport : 1;
  266. UINT64 Avx512VBmiSupport : 1;
  267. UINT64 Avx512VBmi2Support : 1;
  268. UINT64 Avx512VnniSupport : 1;
  269. UINT64 GfniSupport : 1;
  270. UINT64 VaesSupport : 1;
  271. UINT64 Avx512VPopcntdqSupport : 1;
  272. UINT64 VpclmulqdqSupport : 1;
  273. UINT64 Avx512Bf16Support : 1;
  274. UINT64 Avx512Vp2IntersectSupport : 1;
  275. UINT64 Avx512Fp16Support : 1;
  276. UINT64 XfdSupport : 1;
  277. UINT64 AmxTileSupport : 1;
  278. UINT64 AmxBf16Support : 1;
  279. UINT64 AmxInt8Support : 1;
  280. UINT64 AvxVnniSupport : 1;
  281. UINT64 Reserved : 33;
  282. };
  283. UINT64 AsUINT64;
  284. } WHV_PROCESSOR_XSAVE_FEATURES, *PWHV_PROCESSOR_XSAVE_FEATURES;
  285. C_ASSERT(sizeof(WHV_PROCESSOR_XSAVE_FEATURES) == sizeof(UINT64));
  286. typedef union WHV_PROCESSOR_PERFMON_FEATURES {
  287. __C89_NAMELESS struct {
  288. UINT64 PmuSupport : 1;
  289. UINT64 LbrSupport : 1;
  290. UINT64 Reserved : 62;
  291. };
  292. UINT64 AsUINT64;
  293. } WHV_PROCESSOR_PERFMON_FEATURES, *PWHV_PROCESSOR_PERFMON_FEATURES;
  294. C_ASSERT(sizeof(WHV_PROCESSOR_PERFMON_FEATURES) == 8);
  295. typedef union WHV_X64_MSR_EXIT_BITMAP {
  296. UINT64 AsUINT64;
  297. __C89_NAMELESS struct {
  298. UINT64 UnhandledMsrs : 1;
  299. UINT64 TscMsrWrite : 1;
  300. UINT64 TscMsrRead : 1;
  301. UINT64 ApicBaseMsrWrite : 1;
  302. UINT64 MiscEnableMsrRead:1;
  303. UINT64 McUpdatePatchLevelMsrRead:1;
  304. UINT64 Reserved:58;
  305. };
  306. } WHV_X64_MSR_EXIT_BITMAP;
  307. C_ASSERT(sizeof(WHV_X64_MSR_EXIT_BITMAP) == sizeof(UINT64));
  308. typedef struct WHV_MEMORY_RANGE_ENTRY {
  309. UINT64 GuestAddress;
  310. UINT64 SizeInBytes;
  311. } WHV_MEMORY_RANGE_ENTRY;
  312. C_ASSERT(sizeof(WHV_MEMORY_RANGE_ENTRY) == 16);
  313. typedef union WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS {
  314. UINT32 AsUINT32;
  315. __C89_NAMELESS struct {
  316. UINT32 Prefetch:1;
  317. UINT32 AvoidHardFaults:1;
  318. UINT32 Reserved:30;
  319. };
  320. } WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS;
  321. C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS) == 4);
  322. typedef enum WHV_MEMORY_ACCESS_TYPE {
  323. WHvMemoryAccessRead = 0,
  324. WHvMemoryAccessWrite = 1,
  325. WHvMemoryAccessExecute = 2
  326. } WHV_MEMORY_ACCESS_TYPE;
  327. typedef struct WHV_ADVISE_GPA_RANGE_POPULATE {
  328. WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS Flags;
  329. WHV_MEMORY_ACCESS_TYPE AccessType;
  330. } WHV_ADVISE_GPA_RANGE_POPULATE;
  331. C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE_POPULATE) == 8);
  332. typedef struct WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP {
  333. UINT32 IsSupported:1;
  334. UINT32 Reserved:31;
  335. UINT32 HighestFrequencyMhz;
  336. UINT32 NominalFrequencyMhz;
  337. UINT32 LowestFrequencyMhz;
  338. UINT32 FrequencyStepMhz;
  339. } WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP;
  340. C_ASSERT(sizeof(WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP) == 20);
  341. typedef union WHV_SCHEDULER_FEATURES {
  342. __C89_NAMELESS struct {
  343. UINT64 CpuReserve: 1;
  344. UINT64 CpuCap: 1;
  345. UINT64 CpuWeight: 1;
  346. UINT64 CpuGroupId: 1;
  347. UINT64 DisableSmt: 1;
  348. UINT64 Reserved: 59;
  349. };
  350. UINT64 AsUINT64;
  351. } WHV_SCHEDULER_FEATURES;
  352. C_ASSERT(sizeof(WHV_SCHEDULER_FEATURES) == 8);
  353. typedef union WHV_CAPABILITY {
  354. WINBOOL HypervisorPresent;
  355. WHV_CAPABILITY_FEATURES Features;
  356. WHV_EXTENDED_VM_EXITS ExtendedVmExits;
  357. WHV_PROCESSOR_VENDOR ProcessorVendor;
  358. WHV_PROCESSOR_FEATURES ProcessorFeatures;
  359. WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS SyntheticProcessorFeaturesBanks;
  360. WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
  361. UINT8 ProcessorClFlushSize;
  362. UINT64 ExceptionExitBitmap;
  363. WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
  364. UINT64 ProcessorClockFrequency;
  365. UINT64 InterruptClockFrequency;
  366. WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
  367. WHV_ADVISE_GPA_RANGE_POPULATE_FLAGS GpaRangePopulateFlags;
  368. WHV_CAPABILITY_PROCESSOR_FREQUENCY_CAP ProcessorFrequencyCap;
  369. WHV_PROCESSOR_PERFMON_FEATURES ProcessorPerfmonFeatures;
  370. WHV_SCHEDULER_FEATURES SchedulerFeatures;
  371. } WHV_CAPABILITY;
  372. typedef VOID* WHV_PARTITION_HANDLE;
  373. typedef enum WHV_PARTITION_PROPERTY_CODE {
  374. WHvPartitionPropertyCodeExtendedVmExits = 0x00000001,
  375. WHvPartitionPropertyCodeExceptionExitBitmap = 0x00000002,
  376. WHvPartitionPropertyCodeSeparateSecurityDomain = 0x00000003,
  377. WHvPartitionPropertyCodeNestedVirtualization = 0x00000004,
  378. WHvPartitionPropertyCodeX64MsrExitBitmap = 0x00000005,
  379. WHvPartitionPropertyCodePrimaryNumaNode = 0x00000006,
  380. WHvPartitionPropertyCodeCpuReserve = 0x00000007,
  381. WHvPartitionPropertyCodeCpuCap = 0x00000008,
  382. WHvPartitionPropertyCodeCpuWeight = 0x00000009,
  383. WHvPartitionPropertyCodeCpuGroupId = 0x0000000A,
  384. WHvPartitionPropertyCodeProcessorFrequencyCap = 0x0000000B,
  385. WHvPartitionPropertyCodeAllowDeviceAssignment = 0x0000000C,
  386. WHvPartitionPropertyCodeDisableSmt = 0x0000000D,
  387. WHvPartitionPropertyCodeProcessorFeatures = 0x00001001,
  388. WHvPartitionPropertyCodeProcessorClFlushSize = 0x00001002,
  389. WHvPartitionPropertyCodeCpuidExitList = 0x00001003,
  390. WHvPartitionPropertyCodeCpuidResultList = 0x00001004,
  391. WHvPartitionPropertyCodeLocalApicEmulationMode = 0x00001005,
  392. WHvPartitionPropertyCodeProcessorXsaveFeatures = 0x00001006,
  393. WHvPartitionPropertyCodeProcessorClockFrequency = 0x00001007,
  394. WHvPartitionPropertyCodeInterruptClockFrequency = 0x00001008,
  395. WHvPartitionPropertyCodeApicRemoteReadSupport = 0x00001009,
  396. WHvPartitionPropertyCodeProcessorFeaturesBanks = 0x0000100A,
  397. WHvPartitionPropertyCodeReferenceTime = 0x0000100B,
  398. WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks = 0x0000100C,
  399. WHvPartitionPropertyCodeCpuidResultList2 = 0x0000100D,
  400. WHvPartitionPropertyCodeProcessorPerfmonFeatures = 0x0000100E,
  401. WHvPartitionPropertyCodeMsrActionList = 0x0000100F,
  402. WHvPartitionPropertyCodeUnimplementedMsrAction = 0x00001010,
  403. WHvPartitionPropertyCodeProcessorCount = 0x00001fff
  404. } WHV_PARTITION_PROPERTY_CODE;
  405. typedef struct WHV_X64_CPUID_RESULT {
  406. UINT32 Function;
  407. UINT32 Reserved[3];
  408. UINT32 Eax;
  409. UINT32 Ebx;
  410. UINT32 Ecx;
  411. UINT32 Edx;
  412. } WHV_X64_CPUID_RESULT;
  413. C_ASSERT(sizeof(WHV_X64_CPUID_RESULT) == 32);
  414. typedef enum WHV_X64_CPUID_RESULT2_FLAGS {
  415. WHvX64CpuidResult2FlagSubleafSpecific = 0x00000001,
  416. WHvX64CpuidResult2FlagVpSpecific = 0x00000002
  417. } WHV_X64_CPUID_RESULT2_FLAGS;
  418. DEFINE_ENUM_FLAG_OPERATORS(WHV_X64_CPUID_RESULT2_FLAGS);
  419. typedef struct WHV_CPUID_OUTPUT {
  420. UINT32 Eax;
  421. UINT32 Ebx;
  422. UINT32 Ecx;
  423. UINT32 Edx;
  424. } WHV_CPUID_OUTPUT;
  425. C_ASSERT(sizeof(WHV_CPUID_OUTPUT) == 16);
  426. typedef struct WHV_X64_CPUID_RESULT2 {
  427. UINT32 Function;
  428. UINT32 Index;
  429. UINT32 VpIndex;
  430. WHV_X64_CPUID_RESULT2_FLAGS Flags;
  431. WHV_CPUID_OUTPUT Output;
  432. WHV_CPUID_OUTPUT Mask;
  433. } WHV_X64_CPUID_RESULT2;
  434. C_ASSERT(sizeof(WHV_X64_CPUID_RESULT2) == 48);
  435. typedef struct WHV_MSR_ACTION_ENTRY {
  436. UINT32 Index;
  437. UINT8 ReadAction;
  438. UINT8 WriteAction;
  439. UINT16 Reserved;
  440. } WHV_MSR_ACTION_ENTRY;
  441. C_ASSERT(sizeof(WHV_MSR_ACTION_ENTRY) == 8);
  442. typedef enum WHV_MSR_ACTION {
  443. WHvMsrActionArchitectureDefault = 0,
  444. WHvMsrActionIgnoreWriteReadZero = 1,
  445. WHvMsrActionExit = 2
  446. } WHV_MSR_ACTION;
  447. typedef enum WHV_EXCEPTION_TYPE {
  448. WHvX64ExceptionTypeDivideErrorFault = 0x0,
  449. WHvX64ExceptionTypeDebugTrapOrFault = 0x1,
  450. WHvX64ExceptionTypeBreakpointTrap = 0x3,
  451. WHvX64ExceptionTypeOverflowTrap = 0x4,
  452. WHvX64ExceptionTypeBoundRangeFault = 0x5,
  453. WHvX64ExceptionTypeInvalidOpcodeFault = 0x6,
  454. WHvX64ExceptionTypeDeviceNotAvailableFault = 0x7,
  455. WHvX64ExceptionTypeDoubleFaultAbort = 0x8,
  456. WHvX64ExceptionTypeInvalidTaskStateSegmentFault = 0x0A,
  457. WHvX64ExceptionTypeSegmentNotPresentFault = 0x0B,
  458. WHvX64ExceptionTypeStackFault = 0x0C,
  459. WHvX64ExceptionTypeGeneralProtectionFault = 0x0D,
  460. WHvX64ExceptionTypePageFault = 0x0E,
  461. WHvX64ExceptionTypeFloatingPointErrorFault = 0x10,
  462. WHvX64ExceptionTypeAlignmentCheckFault = 0x11,
  463. WHvX64ExceptionTypeMachineCheckAbort = 0x12,
  464. WHvX64ExceptionTypeSimdFloatingPointFault = 0x13
  465. } WHV_EXCEPTION_TYPE;
  466. typedef enum WHV_X64_LOCAL_APIC_EMULATION_MODE {
  467. WHvX64LocalApicEmulationModeNone,
  468. WHvX64LocalApicEmulationModeXApic,
  469. WHvX64LocalApicEmulationModeX2Apic
  470. } WHV_X64_LOCAL_APIC_EMULATION_MODE;
  471. typedef union WHV_PARTITION_PROPERTY {
  472. WHV_EXTENDED_VM_EXITS ExtendedVmExits;
  473. WHV_PROCESSOR_FEATURES ProcessorFeatures;
  474. WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS SyntheticProcessorFeaturesBanks;
  475. WHV_PROCESSOR_XSAVE_FEATURES ProcessorXsaveFeatures;
  476. UINT8 ProcessorClFlushSize;
  477. UINT32 ProcessorCount;
  478. UINT32 CpuidExitList[1];
  479. WHV_X64_CPUID_RESULT CpuidResultList[1];
  480. WHV_X64_CPUID_RESULT2 CpuidResultList2[1];
  481. WHV_MSR_ACTION_ENTRY MsrActionList[1];
  482. WHV_MSR_ACTION UnimplementedMsrAction;
  483. UINT64 ExceptionExitBitmap;
  484. WHV_X64_LOCAL_APIC_EMULATION_MODE LocalApicEmulationMode;
  485. WINBOOL SeparateSecurityDomain;
  486. WINBOOL NestedVirtualization;
  487. WHV_X64_MSR_EXIT_BITMAP X64MsrExitBitmap;
  488. UINT64 ProcessorClockFrequency;
  489. UINT64 InterruptClockFrequency;
  490. WINBOOL ApicRemoteRead;
  491. WHV_PROCESSOR_FEATURES_BANKS ProcessorFeaturesBanks;
  492. UINT64 ReferenceTime;
  493. USHORT PrimaryNumaNode;
  494. UINT32 CpuReserve;
  495. UINT32 CpuCap;
  496. UINT32 CpuWeight;
  497. UINT64 CpuGroupId;
  498. UINT32 ProcessorFrequencyCap;
  499. WINBOOL AllowDeviceAssignment;
  500. WHV_PROCESSOR_PERFMON_FEATURES ProcessorPerfmonFeatures;
  501. WINBOOL DisableSmt;
  502. } WHV_PARTITION_PROPERTY;
  503. typedef UINT64 WHV_GUEST_PHYSICAL_ADDRESS;
  504. typedef UINT64 WHV_GUEST_VIRTUAL_ADDRESS;
  505. typedef enum WHV_MAP_GPA_RANGE_FLAGS {
  506. WHvMapGpaRangeFlagNone = 0x00000000,
  507. WHvMapGpaRangeFlagRead = 0x00000001,
  508. WHvMapGpaRangeFlagWrite = 0x00000002,
  509. WHvMapGpaRangeFlagExecute = 0x00000004,
  510. WHvMapGpaRangeFlagTrackDirtyPages = 0x00000008
  511. } WHV_MAP_GPA_RANGE_FLAGS;
  512. DEFINE_ENUM_FLAG_OPERATORS(WHV_MAP_GPA_RANGE_FLAGS);
  513. typedef enum WHV_TRANSLATE_GVA_FLAGS {
  514. WHvTranslateGvaFlagNone = 0x00000000,
  515. WHvTranslateGvaFlagValidateRead = 0x00000001,
  516. WHvTranslateGvaFlagValidateWrite = 0x00000002,
  517. WHvTranslateGvaFlagValidateExecute = 0x00000004,
  518. WHvTranslateGvaFlagPrivilegeExempt = 0x00000008,
  519. WHvTranslateGvaFlagSetPageTableBits = 0x00000010,
  520. WHvTranslateGvaFlagEnforceSmap = 0x00000100,
  521. WHvTranslateGvaFlagOverrideSmap = 0x00000200
  522. } WHV_TRANSLATE_GVA_FLAGS;
  523. DEFINE_ENUM_FLAG_OPERATORS(WHV_TRANSLATE_GVA_FLAGS);
  524. typedef enum WHV_TRANSLATE_GVA_RESULT_CODE {
  525. WHvTranslateGvaResultSuccess = 0,
  526. WHvTranslateGvaResultPageNotPresent = 1,
  527. WHvTranslateGvaResultPrivilegeViolation = 2,
  528. WHvTranslateGvaResultInvalidPageTableFlags = 3,
  529. WHvTranslateGvaResultGpaUnmapped = 4,
  530. WHvTranslateGvaResultGpaNoReadAccess = 5,
  531. WHvTranslateGvaResultGpaNoWriteAccess = 6,
  532. WHvTranslateGvaResultGpaIllegalOverlayAccess = 7,
  533. WHvTranslateGvaResultIntercept = 8
  534. } WHV_TRANSLATE_GVA_RESULT_CODE;
  535. typedef struct WHV_TRANSLATE_GVA_RESULT {
  536. WHV_TRANSLATE_GVA_RESULT_CODE ResultCode;
  537. UINT32 Reserved;
  538. } WHV_TRANSLATE_GVA_RESULT;
  539. C_ASSERT(sizeof(WHV_TRANSLATE_GVA_RESULT) == 8);
  540. typedef union WHV_ADVISE_GPA_RANGE {
  541. WHV_ADVISE_GPA_RANGE_POPULATE Populate;
  542. } WHV_ADVISE_GPA_RANGE;
  543. C_ASSERT(sizeof(WHV_ADVISE_GPA_RANGE) == 8);
  544. typedef enum WHV_CACHE_TYPE {
  545. WHvCacheTypeUncached = 0,
  546. WHvCacheTypeWriteCombining = 1,
  547. WHvCacheTypeWriteThrough = 4,
  548. #ifdef __x86_64__
  549. WHvCacheTypeWriteProtected = 5,
  550. #endif
  551. WHvCacheTypeWriteBack = 6
  552. } WHV_CACHE_TYPE;
  553. typedef union WHV_ACCESS_GPA_CONTROLS {
  554. UINT64 AsUINT64;
  555. __C89_NAMELESS struct {
  556. WHV_CACHE_TYPE CacheType;
  557. UINT32 Reserved;
  558. };
  559. } WHV_ACCESS_GPA_CONTROLS;
  560. C_ASSERT(sizeof(WHV_ACCESS_GPA_CONTROLS) == 8);
  561. #define WHV_READ_WRITE_GPA_RANGE_MAX_SIZE 16
  562. typedef enum WHV_REGISTER_NAME {
  563. WHvX64RegisterRax = 0x00000000,
  564. WHvX64RegisterRcx = 0x00000001,
  565. WHvX64RegisterRdx = 0x00000002,
  566. WHvX64RegisterRbx = 0x00000003,
  567. WHvX64RegisterRsp = 0x00000004,
  568. WHvX64RegisterRbp = 0x00000005,
  569. WHvX64RegisterRsi = 0x00000006,
  570. WHvX64RegisterRdi = 0x00000007,
  571. WHvX64RegisterR8 = 0x00000008,
  572. WHvX64RegisterR9 = 0x00000009,
  573. WHvX64RegisterR10 = 0x0000000A,
  574. WHvX64RegisterR11 = 0x0000000B,
  575. WHvX64RegisterR12 = 0x0000000C,
  576. WHvX64RegisterR13 = 0x0000000D,
  577. WHvX64RegisterR14 = 0x0000000E,
  578. WHvX64RegisterR15 = 0x0000000F,
  579. WHvX64RegisterRip = 0x00000010,
  580. WHvX64RegisterRflags = 0x00000011,
  581. WHvX64RegisterEs = 0x00000012,
  582. WHvX64RegisterCs = 0x00000013,
  583. WHvX64RegisterSs = 0x00000014,
  584. WHvX64RegisterDs = 0x00000015,
  585. WHvX64RegisterFs = 0x00000016,
  586. WHvX64RegisterGs = 0x00000017,
  587. WHvX64RegisterLdtr = 0x00000018,
  588. WHvX64RegisterTr = 0x00000019,
  589. WHvX64RegisterIdtr = 0x0000001A,
  590. WHvX64RegisterGdtr = 0x0000001B,
  591. WHvX64RegisterCr0 = 0x0000001C,
  592. WHvX64RegisterCr2 = 0x0000001D,
  593. WHvX64RegisterCr3 = 0x0000001E,
  594. WHvX64RegisterCr4 = 0x0000001F,
  595. WHvX64RegisterCr8 = 0x00000020,
  596. WHvX64RegisterDr0 = 0x00000021,
  597. WHvX64RegisterDr1 = 0x00000022,
  598. WHvX64RegisterDr2 = 0x00000023,
  599. WHvX64RegisterDr3 = 0x00000024,
  600. WHvX64RegisterDr6 = 0x00000025,
  601. WHvX64RegisterDr7 = 0x00000026,
  602. WHvX64RegisterXCr0 = 0x00000027,
  603. WHvX64RegisterVirtualCr0 = 0x00000028,
  604. WHvX64RegisterVirtualCr3 = 0x00000029,
  605. WHvX64RegisterVirtualCr4 = 0x0000002A,
  606. WHvX64RegisterVirtualCr8 = 0x0000002B,
  607. WHvX64RegisterXmm0 = 0x00001000,
  608. WHvX64RegisterXmm1 = 0x00001001,
  609. WHvX64RegisterXmm2 = 0x00001002,
  610. WHvX64RegisterXmm3 = 0x00001003,
  611. WHvX64RegisterXmm4 = 0x00001004,
  612. WHvX64RegisterXmm5 = 0x00001005,
  613. WHvX64RegisterXmm6 = 0x00001006,
  614. WHvX64RegisterXmm7 = 0x00001007,
  615. WHvX64RegisterXmm8 = 0x00001008,
  616. WHvX64RegisterXmm9 = 0x00001009,
  617. WHvX64RegisterXmm10 = 0x0000100A,
  618. WHvX64RegisterXmm11 = 0x0000100B,
  619. WHvX64RegisterXmm12 = 0x0000100C,
  620. WHvX64RegisterXmm13 = 0x0000100D,
  621. WHvX64RegisterXmm14 = 0x0000100E,
  622. WHvX64RegisterXmm15 = 0x0000100F,
  623. WHvX64RegisterFpMmx0 = 0x00001010,
  624. WHvX64RegisterFpMmx1 = 0x00001011,
  625. WHvX64RegisterFpMmx2 = 0x00001012,
  626. WHvX64RegisterFpMmx3 = 0x00001013,
  627. WHvX64RegisterFpMmx4 = 0x00001014,
  628. WHvX64RegisterFpMmx5 = 0x00001015,
  629. WHvX64RegisterFpMmx6 = 0x00001016,
  630. WHvX64RegisterFpMmx7 = 0x00001017,
  631. WHvX64RegisterFpControlStatus = 0x00001018,
  632. WHvX64RegisterXmmControlStatus = 0x00001019,
  633. WHvX64RegisterTsc = 0x00002000,
  634. WHvX64RegisterEfer = 0x00002001,
  635. WHvX64RegisterKernelGsBase = 0x00002002,
  636. WHvX64RegisterApicBase = 0x00002003,
  637. WHvX64RegisterPat = 0x00002004,
  638. WHvX64RegisterSysenterCs = 0x00002005,
  639. WHvX64RegisterSysenterEip = 0x00002006,
  640. WHvX64RegisterSysenterEsp = 0x00002007,
  641. WHvX64RegisterStar = 0x00002008,
  642. WHvX64RegisterLstar = 0x00002009,
  643. WHvX64RegisterCstar = 0x0000200A,
  644. WHvX64RegisterSfmask = 0x0000200B,
  645. WHvX64RegisterInitialApicId = 0x0000200C,
  646. WHvX64RegisterMsrMtrrCap = 0x0000200D,
  647. WHvX64RegisterMsrMtrrDefType = 0x0000200E,
  648. WHvX64RegisterMsrMtrrPhysBase0 = 0x00002010,
  649. WHvX64RegisterMsrMtrrPhysBase1 = 0x00002011,
  650. WHvX64RegisterMsrMtrrPhysBase2 = 0x00002012,
  651. WHvX64RegisterMsrMtrrPhysBase3 = 0x00002013,
  652. WHvX64RegisterMsrMtrrPhysBase4 = 0x00002014,
  653. WHvX64RegisterMsrMtrrPhysBase5 = 0x00002015,
  654. WHvX64RegisterMsrMtrrPhysBase6 = 0x00002016,
  655. WHvX64RegisterMsrMtrrPhysBase7 = 0x00002017,
  656. WHvX64RegisterMsrMtrrPhysBase8 = 0x00002018,
  657. WHvX64RegisterMsrMtrrPhysBase9 = 0x00002019,
  658. WHvX64RegisterMsrMtrrPhysBaseA = 0x0000201A,
  659. WHvX64RegisterMsrMtrrPhysBaseB = 0x0000201B,
  660. WHvX64RegisterMsrMtrrPhysBaseC = 0x0000201C,
  661. WHvX64RegisterMsrMtrrPhysBaseD = 0x0000201D,
  662. WHvX64RegisterMsrMtrrPhysBaseE = 0x0000201E,
  663. WHvX64RegisterMsrMtrrPhysBaseF = 0x0000201F,
  664. WHvX64RegisterMsrMtrrPhysMask0 = 0x00002040,
  665. WHvX64RegisterMsrMtrrPhysMask1 = 0x00002041,
  666. WHvX64RegisterMsrMtrrPhysMask2 = 0x00002042,
  667. WHvX64RegisterMsrMtrrPhysMask3 = 0x00002043,
  668. WHvX64RegisterMsrMtrrPhysMask4 = 0x00002044,
  669. WHvX64RegisterMsrMtrrPhysMask5 = 0x00002045,
  670. WHvX64RegisterMsrMtrrPhysMask6 = 0x00002046,
  671. WHvX64RegisterMsrMtrrPhysMask7 = 0x00002047,
  672. WHvX64RegisterMsrMtrrPhysMask8 = 0x00002048,
  673. WHvX64RegisterMsrMtrrPhysMask9 = 0x00002049,
  674. WHvX64RegisterMsrMtrrPhysMaskA = 0x0000204A,
  675. WHvX64RegisterMsrMtrrPhysMaskB = 0x0000204B,
  676. WHvX64RegisterMsrMtrrPhysMaskC = 0x0000204C,
  677. WHvX64RegisterMsrMtrrPhysMaskD = 0x0000204D,
  678. WHvX64RegisterMsrMtrrPhysMaskE = 0x0000204E,
  679. WHvX64RegisterMsrMtrrPhysMaskF = 0x0000204F,
  680. WHvX64RegisterMsrMtrrFix64k00000 = 0x00002070,
  681. WHvX64RegisterMsrMtrrFix16k80000 = 0x00002071,
  682. WHvX64RegisterMsrMtrrFix16kA0000 = 0x00002072,
  683. WHvX64RegisterMsrMtrrFix4kC0000 = 0x00002073,
  684. WHvX64RegisterMsrMtrrFix4kC8000 = 0x00002074,
  685. WHvX64RegisterMsrMtrrFix4kD0000 = 0x00002075,
  686. WHvX64RegisterMsrMtrrFix4kD8000 = 0x00002076,
  687. WHvX64RegisterMsrMtrrFix4kE0000 = 0x00002077,
  688. WHvX64RegisterMsrMtrrFix4kE8000 = 0x00002078,
  689. WHvX64RegisterMsrMtrrFix4kF0000 = 0x00002079,
  690. WHvX64RegisterMsrMtrrFix4kF8000 = 0x0000207A,
  691. WHvX64RegisterTscAux = 0x0000207B,
  692. WHvX64RegisterBndcfgs = 0x0000207C,
  693. WHvX64RegisterMCount = 0x0000207E,
  694. WHvX64RegisterACount = 0x0000207F,
  695. WHvX64RegisterSpecCtrl = 0x00002084,
  696. WHvX64RegisterPredCmd = 0x00002085,
  697. WHvX64RegisterTscVirtualOffset = 0x00002087,
  698. WHvX64RegisterTsxCtrl = 0x00002088,
  699. WHvX64RegisterXss = 0x0000208B,
  700. WHvX64RegisterUCet = 0x0000208C,
  701. WHvX64RegisterSCet = 0x0000208D,
  702. WHvX64RegisterSsp = 0x0000208E,
  703. WHvX64RegisterPl0Ssp = 0x0000208F,
  704. WHvX64RegisterPl1Ssp = 0x00002090,
  705. WHvX64RegisterPl2Ssp = 0x00002091,
  706. WHvX64RegisterPl3Ssp = 0x00002092,
  707. WHvX64RegisterInterruptSspTableAddr = 0x00002093,
  708. WHvX64RegisterTscDeadline = 0x00002095,
  709. WHvX64RegisterTscAdjust = 0x00002096,
  710. WHvX64RegisterUmwaitControl = 0x00002098,
  711. WHvX64RegisterXfd = 0x00002099,
  712. WHvX64RegisterXfdErr = 0x0000209A,
  713. WHvX64RegisterApicId = 0x00003002,
  714. WHvX64RegisterApicVersion = 0x00003003,
  715. WHvX64RegisterApicTpr = 0x00003008,
  716. WHvX64RegisterApicPpr = 0x0000300A,
  717. WHvX64RegisterApicEoi = 0x0000300B,
  718. WHvX64RegisterApicLdr = 0x0000300D,
  719. WHvX64RegisterApicSpurious = 0x0000300F,
  720. WHvX64RegisterApicIsr0 = 0x00003010,
  721. WHvX64RegisterApicIsr1 = 0x00003011,
  722. WHvX64RegisterApicIsr2 = 0x00003012,
  723. WHvX64RegisterApicIsr3 = 0x00003013,
  724. WHvX64RegisterApicIsr4 = 0x00003014,
  725. WHvX64RegisterApicIsr5 = 0x00003015,
  726. WHvX64RegisterApicIsr6 = 0x00003016,
  727. WHvX64RegisterApicIsr7 = 0x00003017,
  728. WHvX64RegisterApicTmr0 = 0x00003018,
  729. WHvX64RegisterApicTmr1 = 0x00003019,
  730. WHvX64RegisterApicTmr2 = 0x0000301A,
  731. WHvX64RegisterApicTmr3 = 0x0000301B,
  732. WHvX64RegisterApicTmr4 = 0x0000301C,
  733. WHvX64RegisterApicTmr5 = 0x0000301D,
  734. WHvX64RegisterApicTmr6 = 0x0000301E,
  735. WHvX64RegisterApicTmr7 = 0x0000301F,
  736. WHvX64RegisterApicIrr0 = 0x00003020,
  737. WHvX64RegisterApicIrr1 = 0x00003021,
  738. WHvX64RegisterApicIrr2 = 0x00003022,
  739. WHvX64RegisterApicIrr3 = 0x00003023,
  740. WHvX64RegisterApicIrr4 = 0x00003024,
  741. WHvX64RegisterApicIrr5 = 0x00003025,
  742. WHvX64RegisterApicIrr6 = 0x00003026,
  743. WHvX64RegisterApicIrr7 = 0x00003027,
  744. WHvX64RegisterApicEse = 0x00003028,
  745. WHvX64RegisterApicIcr = 0x00003030,
  746. WHvX64RegisterApicLvtTimer = 0x00003032,
  747. WHvX64RegisterApicLvtThermal = 0x00003033,
  748. WHvX64RegisterApicLvtPerfmon = 0x00003034,
  749. WHvX64RegisterApicLvtLint0 = 0x00003035,
  750. WHvX64RegisterApicLvtLint1 = 0x00003036,
  751. WHvX64RegisterApicLvtError = 0x00003037,
  752. WHvX64RegisterApicInitCount = 0x00003038,
  753. WHvX64RegisterApicCurrentCount = 0x00003039,
  754. WHvX64RegisterApicDivide = 0x0000303E,
  755. WHvX64RegisterApicSelfIpi = 0x0000303F,
  756. WHvRegisterSint0 = 0x00004000,
  757. WHvRegisterSint1 = 0x00004001,
  758. WHvRegisterSint2 = 0x00004002,
  759. WHvRegisterSint3 = 0x00004003,
  760. WHvRegisterSint4 = 0x00004004,
  761. WHvRegisterSint5 = 0x00004005,
  762. WHvRegisterSint6 = 0x00004006,
  763. WHvRegisterSint7 = 0x00004007,
  764. WHvRegisterSint8 = 0x00004008,
  765. WHvRegisterSint9 = 0x00004009,
  766. WHvRegisterSint10 = 0x0000400A,
  767. WHvRegisterSint11 = 0x0000400B,
  768. WHvRegisterSint12 = 0x0000400C,
  769. WHvRegisterSint13 = 0x0000400D,
  770. WHvRegisterSint14 = 0x0000400E,
  771. WHvRegisterSint15 = 0x0000400F,
  772. WHvRegisterScontrol = 0x00004010,
  773. WHvRegisterSversion = 0x00004011,
  774. WHvRegisterSiefp = 0x00004012,
  775. WHvRegisterSimp = 0x00004013,
  776. WHvRegisterEom = 0x00004014,
  777. WHvRegisterVpRuntime = 0x00005000,
  778. WHvX64RegisterHypercall = 0x00005001,
  779. WHvRegisterGuestOsId = 0x00005002,
  780. WHvRegisterVpAssistPage = 0x00005013,
  781. WHvRegisterReferenceTsc = 0x00005017,
  782. WHvRegisterReferenceTscSequence = 0x0000501A,
  783. WHvRegisterPendingInterruption = 0x80000000,
  784. WHvRegisterInterruptState = 0x80000001,
  785. WHvRegisterPendingEvent = 0x80000002,
  786. WHvX64RegisterDeliverabilityNotifications = 0x80000004,
  787. WHvRegisterInternalActivityState = 0x80000005,
  788. WHvX64RegisterPendingDebugException = 0x80000006
  789. } WHV_REGISTER_NAME;
  790. typedef union DECLSPEC_ALIGN(16) WHV_UINT128 {
  791. __C89_NAMELESS struct {
  792. UINT64 Low64;
  793. UINT64 High64;
  794. };
  795. UINT32 Dword[4];
  796. } WHV_UINT128;
  797. C_ASSERT(sizeof(WHV_UINT128) == 16);
  798. typedef union WHV_X64_FP_REGISTER {
  799. __C89_NAMELESS struct {
  800. UINT64 Mantissa;
  801. UINT64 BiasedExponent:15;
  802. UINT64 Sign:1;
  803. UINT64 Reserved:48;
  804. };
  805. WHV_UINT128 AsUINT128;
  806. } WHV_X64_FP_REGISTER;
  807. C_ASSERT(sizeof(WHV_X64_FP_REGISTER) == 16);
  808. typedef union WHV_X64_FP_CONTROL_STATUS_REGISTER {
  809. __C89_NAMELESS struct {
  810. UINT16 FpControl;
  811. UINT16 FpStatus;
  812. UINT8 FpTag;
  813. UINT8 Reserved;
  814. UINT16 LastFpOp;
  815. __C89_NAMELESS union {
  816. UINT64 LastFpRip;
  817. __C89_NAMELESS struct {
  818. UINT32 LastFpEip;
  819. UINT16 LastFpCs;
  820. UINT16 Reserved2;
  821. };
  822. };
  823. };
  824. WHV_UINT128 AsUINT128;
  825. } WHV_X64_FP_CONTROL_STATUS_REGISTER;
  826. C_ASSERT(sizeof(WHV_X64_FP_CONTROL_STATUS_REGISTER) == 16);
  827. typedef union WHV_X64_XMM_CONTROL_STATUS_REGISTER {
  828. __C89_NAMELESS struct {
  829. __C89_NAMELESS union {
  830. UINT64 LastFpRdp;
  831. __C89_NAMELESS struct {
  832. UINT32 LastFpDp;
  833. UINT16 LastFpDs;
  834. UINT16 Reserved;
  835. };
  836. };
  837. UINT32 XmmStatusControl;
  838. UINT32 XmmStatusControlMask;
  839. };
  840. WHV_UINT128 AsUINT128;
  841. } WHV_X64_XMM_CONTROL_STATUS_REGISTER;
  842. C_ASSERT(sizeof(WHV_X64_FP_CONTROL_STATUS_REGISTER) == 16);
  843. typedef struct WHV_X64_SEGMENT_REGISTER {
  844. UINT64 Base;
  845. UINT32 Limit;
  846. UINT16 Selector;
  847. __C89_NAMELESS union {
  848. __C89_NAMELESS struct {
  849. UINT16 SegmentType:4;
  850. UINT16 NonSystemSegment:1;
  851. UINT16 DescriptorPrivilegeLevel:2;
  852. UINT16 Present:1;
  853. UINT16 Reserved:4;
  854. UINT16 Available:1;
  855. UINT16 Long:1;
  856. UINT16 Default:1;
  857. UINT16 Granularity:1;
  858. };
  859. UINT16 Attributes;
  860. };
  861. } WHV_X64_SEGMENT_REGISTER;
  862. C_ASSERT(sizeof(WHV_X64_SEGMENT_REGISTER) == 16);
  863. typedef struct WHV_X64_TABLE_REGISTER {
  864. UINT16 Pad[3];
  865. UINT16 Limit;
  866. UINT64 Base;
  867. } WHV_X64_TABLE_REGISTER;
  868. C_ASSERT(sizeof(WHV_X64_TABLE_REGISTER) == 16);
  869. typedef union WHV_X64_INTERRUPT_STATE_REGISTER {
  870. __C89_NAMELESS struct {
  871. UINT64 InterruptShadow:1;
  872. UINT64 NmiMasked:1;
  873. UINT64 Reserved:62;
  874. };
  875. UINT64 AsUINT64;
  876. } WHV_X64_INTERRUPT_STATE_REGISTER;
  877. C_ASSERT(sizeof(WHV_X64_INTERRUPT_STATE_REGISTER) == 8);
  878. typedef union WHV_X64_PENDING_INTERRUPTION_REGISTER {
  879. __C89_NAMELESS struct {
  880. UINT32 InterruptionPending:1;
  881. UINT32 InterruptionType:3;
  882. UINT32 DeliverErrorCode:1;
  883. UINT32 InstructionLength:4;
  884. UINT32 NestedEvent:1;
  885. UINT32 Reserved:6;
  886. UINT32 InterruptionVector:16;
  887. UINT32 ErrorCode;
  888. };
  889. UINT64 AsUINT64;
  890. } WHV_X64_PENDING_INTERRUPTION_REGISTER;
  891. C_ASSERT(sizeof(WHV_X64_PENDING_INTERRUPTION_REGISTER) == sizeof(UINT64));
  892. typedef union WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER {
  893. __C89_NAMELESS struct {
  894. UINT64 NmiNotification:1;
  895. UINT64 InterruptNotification:1;
  896. UINT64 InterruptPriority:4;
  897. UINT64 Reserved:42;
  898. UINT64 Sint:16;
  899. };
  900. UINT64 AsUINT64;
  901. } WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER;
  902. C_ASSERT(sizeof(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) == sizeof(UINT64));
  903. typedef enum WHV_X64_PENDING_EVENT_TYPE {
  904. WHvX64PendingEventException = 0,
  905. WHvX64PendingEventExtInt = 5
  906. } WHV_X64_PENDING_EVENT_TYPE;
  907. typedef union WHV_X64_PENDING_EXCEPTION_EVENT {
  908. __C89_NAMELESS struct {
  909. UINT32 EventPending : 1;
  910. UINT32 EventType : 3;
  911. UINT32 Reserved0 : 4;
  912. UINT32 DeliverErrorCode : 1;
  913. UINT32 Reserved1 : 7;
  914. UINT32 Vector : 16;
  915. UINT32 ErrorCode;
  916. UINT64 ExceptionParameter;
  917. };
  918. WHV_UINT128 AsUINT128;
  919. } WHV_X64_PENDING_EXCEPTION_EVENT;
  920. C_ASSERT(sizeof(WHV_X64_PENDING_EXCEPTION_EVENT) == sizeof(WHV_UINT128));
  921. typedef union WHV_X64_PENDING_EXT_INT_EVENT {
  922. __C89_NAMELESS struct {
  923. UINT64 EventPending : 1;
  924. UINT64 EventType : 3;
  925. UINT64 Reserved0 : 4;
  926. UINT64 Vector : 8;
  927. UINT64 Reserved1 : 48;
  928. UINT64 Reserved2;
  929. };
  930. WHV_UINT128 AsUINT128;
  931. } WHV_X64_PENDING_EXT_INT_EVENT;
  932. C_ASSERT(sizeof(WHV_X64_PENDING_EXT_INT_EVENT) == sizeof(WHV_UINT128));
  933. typedef union WHV_INTERNAL_ACTIVITY_REGISTER {
  934. __C89_NAMELESS struct {
  935. UINT64 StartupSuspend : 1;
  936. UINT64 HaltSuspend : 1;
  937. UINT64 IdleSuspend : 1;
  938. UINT64 Reserved :61;
  939. };
  940. UINT64 AsUINT64;
  941. } WHV_INTERNAL_ACTIVITY_REGISTER;
  942. C_ASSERT(sizeof(WHV_INTERNAL_ACTIVITY_REGISTER) == sizeof(UINT64));
  943. typedef union WHV_X64_PENDING_DEBUG_EXCEPTION {
  944. UINT64 AsUINT64;
  945. __C89_NAMELESS struct {
  946. UINT64 Breakpoint0 : 1;
  947. UINT64 Breakpoint1 : 1;
  948. UINT64 Breakpoint2 : 1;
  949. UINT64 Breakpoint3 : 1;
  950. UINT64 SingleStep : 1;
  951. UINT64 Reserved0 : 59;
  952. };
  953. } WHV_X64_PENDING_DEBUG_EXCEPTION;
  954. C_ASSERT(sizeof(WHV_X64_PENDING_DEBUG_EXCEPTION) == sizeof(UINT64));
  955. typedef struct WHV_SYNIC_SINT_DELIVERABLE_CONTEXT {
  956. UINT16 DeliverableSints;
  957. UINT16 Reserved1;
  958. UINT32 Reserved2;
  959. } WHV_SYNIC_SINT_DELIVERABLE_CONTEXT;
  960. C_ASSERT(sizeof(WHV_SYNIC_SINT_DELIVERABLE_CONTEXT) == 8);
  961. typedef union WHV_REGISTER_VALUE {
  962. WHV_UINT128 Reg128;
  963. UINT64 Reg64;
  964. UINT32 Reg32;
  965. UINT16 Reg16;
  966. UINT8 Reg8;
  967. WHV_X64_FP_REGISTER Fp;
  968. WHV_X64_FP_CONTROL_STATUS_REGISTER FpControlStatus;
  969. WHV_X64_XMM_CONTROL_STATUS_REGISTER XmmControlStatus;
  970. WHV_X64_SEGMENT_REGISTER Segment;
  971. WHV_X64_TABLE_REGISTER Table;
  972. WHV_X64_INTERRUPT_STATE_REGISTER InterruptState;
  973. WHV_X64_PENDING_INTERRUPTION_REGISTER PendingInterruption;
  974. WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER DeliverabilityNotifications;
  975. WHV_X64_PENDING_EXCEPTION_EVENT ExceptionEvent;
  976. WHV_X64_PENDING_EXT_INT_EVENT ExtIntEvent;
  977. WHV_INTERNAL_ACTIVITY_REGISTER InternalActivity;
  978. WHV_X64_PENDING_DEBUG_EXCEPTION PendingDebugException;
  979. } WHV_REGISTER_VALUE;
  980. C_ASSERT(sizeof(WHV_REGISTER_VALUE) == 16);
  981. typedef enum WHV_RUN_VP_EXIT_REASON {
  982. WHvRunVpExitReasonNone = 0x00000000,
  983. WHvRunVpExitReasonMemoryAccess = 0x00000001,
  984. WHvRunVpExitReasonX64IoPortAccess = 0x00000002,
  985. WHvRunVpExitReasonUnrecoverableException = 0x00000004,
  986. WHvRunVpExitReasonInvalidVpRegisterValue = 0x00000005,
  987. WHvRunVpExitReasonUnsupportedFeature = 0x00000006,
  988. WHvRunVpExitReasonX64InterruptWindow = 0x00000007,
  989. WHvRunVpExitReasonX64Halt = 0x00000008,
  990. WHvRunVpExitReasonX64ApicEoi = 0x00000009,
  991. WHvRunVpExitReasonSynicSintDeliverable = 0x0000000A,
  992. WHvRunVpExitReasonX64MsrAccess = 0x00001000,
  993. WHvRunVpExitReasonX64Cpuid = 0x00001001,
  994. WHvRunVpExitReasonException = 0x00001002,
  995. WHvRunVpExitReasonX64Rdtsc = 0x00001003,
  996. WHvRunVpExitReasonX64ApicSmiTrap = 0x00001004,
  997. WHvRunVpExitReasonHypercall = 0x00001005,
  998. WHvRunVpExitReasonX64ApicInitSipiTrap = 0x00001006,
  999. WHvRunVpExitReasonX64ApicWriteTrap = 0x00001007,
  1000. WHvRunVpExitReasonCanceled = 0x00002001
  1001. } WHV_RUN_VP_EXIT_REASON;
  1002. typedef union WHV_X64_VP_EXECUTION_STATE {
  1003. __C89_NAMELESS struct {
  1004. UINT16 Cpl : 2;
  1005. UINT16 Cr0Pe : 1;
  1006. UINT16 Cr0Am : 1;
  1007. UINT16 EferLma : 1;
  1008. UINT16 DebugActive : 1;
  1009. UINT16 InterruptionPending : 1;
  1010. UINT16 Reserved0 : 5;
  1011. UINT16 InterruptShadow : 1;
  1012. UINT16 Reserved1 : 3;
  1013. };
  1014. UINT16 AsUINT16;
  1015. } WHV_X64_VP_EXECUTION_STATE;
  1016. C_ASSERT(sizeof(WHV_X64_VP_EXECUTION_STATE) == sizeof(UINT16));
  1017. typedef struct WHV_VP_EXIT_CONTEXT {
  1018. WHV_X64_VP_EXECUTION_STATE ExecutionState;
  1019. UINT8 InstructionLength : 4;
  1020. UINT8 Cr8 : 4;
  1021. UINT8 Reserved;
  1022. UINT32 Reserved2;
  1023. WHV_X64_SEGMENT_REGISTER Cs;
  1024. UINT64 Rip;
  1025. UINT64 Rflags;
  1026. } WHV_VP_EXIT_CONTEXT;
  1027. C_ASSERT(sizeof(WHV_VP_EXIT_CONTEXT) == 40);
  1028. typedef union WHV_MEMORY_ACCESS_INFO {
  1029. __C89_NAMELESS struct {
  1030. UINT32 AccessType : 2;
  1031. UINT32 GpaUnmapped : 1;
  1032. UINT32 GvaValid : 1;
  1033. UINT32 Reserved : 28;
  1034. };
  1035. UINT32 AsUINT32;
  1036. } WHV_MEMORY_ACCESS_INFO;
  1037. C_ASSERT(sizeof(WHV_MEMORY_ACCESS_INFO) == 4);
  1038. typedef struct WHV_MEMORY_ACCESS_CONTEXT {
  1039. UINT8 InstructionByteCount;
  1040. UINT8 Reserved[3];
  1041. UINT8 InstructionBytes[16];
  1042. WHV_MEMORY_ACCESS_INFO AccessInfo;
  1043. WHV_GUEST_PHYSICAL_ADDRESS Gpa;
  1044. WHV_GUEST_VIRTUAL_ADDRESS Gva;
  1045. } WHV_MEMORY_ACCESS_CONTEXT;
  1046. C_ASSERT(sizeof(WHV_MEMORY_ACCESS_CONTEXT) == 40);
  1047. typedef union WHV_X64_IO_PORT_ACCESS_INFO {
  1048. __C89_NAMELESS struct {
  1049. UINT32 IsWrite : 1;
  1050. UINT32 AccessSize: 3;
  1051. UINT32 StringOp : 1;
  1052. UINT32 RepPrefix : 1;
  1053. UINT32 Reserved : 26;
  1054. };
  1055. UINT32 AsUINT32;
  1056. } WHV_X64_IO_PORT_ACCESS_INFO;
  1057. C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_INFO) == sizeof(UINT32));
  1058. typedef struct WHV_X64_IO_PORT_ACCESS_CONTEXT {
  1059. UINT8 InstructionByteCount;
  1060. UINT8 Reserved[3];
  1061. UINT8 InstructionBytes[16];
  1062. WHV_X64_IO_PORT_ACCESS_INFO AccessInfo;
  1063. UINT16 PortNumber;
  1064. UINT16 Reserved2[3];
  1065. UINT64 Rax;
  1066. UINT64 Rcx;
  1067. UINT64 Rsi;
  1068. UINT64 Rdi;
  1069. WHV_X64_SEGMENT_REGISTER Ds;
  1070. WHV_X64_SEGMENT_REGISTER Es;
  1071. } WHV_X64_IO_PORT_ACCESS_CONTEXT;
  1072. C_ASSERT(sizeof(WHV_X64_IO_PORT_ACCESS_CONTEXT) == 96);
  1073. typedef union WHV_X64_MSR_ACCESS_INFO {
  1074. __C89_NAMELESS struct {
  1075. UINT32 IsWrite : 1;
  1076. UINT32 Reserved : 31;
  1077. };
  1078. UINT32 AsUINT32;
  1079. } WHV_X64_MSR_ACCESS_INFO;
  1080. C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_INFO) == sizeof(UINT32));
  1081. typedef struct WHV_X64_MSR_ACCESS_CONTEXT {
  1082. WHV_X64_MSR_ACCESS_INFO AccessInfo;
  1083. UINT32 MsrNumber;
  1084. UINT64 Rax;
  1085. UINT64 Rdx;
  1086. } WHV_X64_MSR_ACCESS_CONTEXT;
  1087. C_ASSERT(sizeof(WHV_X64_MSR_ACCESS_CONTEXT) == 24);
  1088. typedef struct WHV_X64_CPUID_ACCESS_CONTEXT {
  1089. UINT64 Rax;
  1090. UINT64 Rcx;
  1091. UINT64 Rdx;
  1092. UINT64 Rbx;
  1093. UINT64 DefaultResultRax;
  1094. UINT64 DefaultResultRcx;
  1095. UINT64 DefaultResultRdx;
  1096. UINT64 DefaultResultRbx;
  1097. } WHV_X64_CPUID_ACCESS_CONTEXT;
  1098. C_ASSERT(sizeof(WHV_X64_CPUID_ACCESS_CONTEXT) == 64);
  1099. typedef union WHV_VP_EXCEPTION_INFO {
  1100. __C89_NAMELESS struct {
  1101. UINT32 ErrorCodeValid : 1;
  1102. UINT32 SoftwareException : 1;
  1103. UINT32 Reserved : 30;
  1104. };
  1105. UINT32 AsUINT32;
  1106. } WHV_VP_EXCEPTION_INFO;
  1107. C_ASSERT(sizeof(WHV_VP_EXCEPTION_INFO) == sizeof(UINT32));
  1108. typedef struct WHV_VP_EXCEPTION_CONTEXT {
  1109. UINT8 InstructionByteCount;
  1110. UINT8 Reserved[3];
  1111. UINT8 InstructionBytes[16];
  1112. WHV_VP_EXCEPTION_INFO ExceptionInfo;
  1113. UINT8 ExceptionType;
  1114. UINT8 Reserved2[3];
  1115. UINT32 ErrorCode;
  1116. UINT64 ExceptionParameter;
  1117. } WHV_VP_EXCEPTION_CONTEXT;
  1118. C_ASSERT(sizeof(WHV_VP_EXCEPTION_CONTEXT) == 40);
  1119. typedef enum WHV_X64_UNSUPPORTED_FEATURE_CODE {
  1120. WHvUnsupportedFeatureIntercept = 1,
  1121. WHvUnsupportedFeatureTaskSwitchTss = 2
  1122. } WHV_X64_UNSUPPORTED_FEATURE_CODE;
  1123. typedef struct WHV_X64_UNSUPPORTED_FEATURE_CONTEXT {
  1124. WHV_X64_UNSUPPORTED_FEATURE_CODE FeatureCode;
  1125. UINT32 Reserved;
  1126. UINT64 FeatureParameter;
  1127. } WHV_X64_UNSUPPORTED_FEATURE_CONTEXT;
  1128. C_ASSERT(sizeof(WHV_X64_UNSUPPORTED_FEATURE_CONTEXT) == 16);
  1129. typedef enum WHV_RUN_VP_CANCEL_REASON {
  1130. WhvRunVpCancelReasonUser = 0
  1131. } WHV_RUN_VP_CANCEL_REASON;
  1132. typedef struct WHV_RUN_VP_CANCELED_CONTEXT {
  1133. WHV_RUN_VP_CANCEL_REASON CancelReason;
  1134. } WHV_RUN_VP_CANCELED_CONTEXT;
  1135. C_ASSERT(sizeof(WHV_RUN_VP_CANCELED_CONTEXT) == 4);
  1136. typedef enum WHV_X64_PENDING_INTERRUPTION_TYPE {
  1137. WHvX64PendingInterrupt = 0,
  1138. WHvX64PendingNmi = 2,
  1139. WHvX64PendingException = 3
  1140. } WHV_X64_PENDING_INTERRUPTION_TYPE, *PWHV_X64_PENDING_INTERRUPTION_TYPE;
  1141. typedef struct WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT {
  1142. WHV_X64_PENDING_INTERRUPTION_TYPE DeliverableType;
  1143. } WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT, *PWHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT;
  1144. C_ASSERT(sizeof(WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT) == 4);
  1145. typedef struct WHV_X64_APIC_EOI_CONTEXT {
  1146. UINT32 InterruptVector;
  1147. } WHV_X64_APIC_EOI_CONTEXT;
  1148. C_ASSERT(sizeof(WHV_X64_APIC_EOI_CONTEXT) == 4);
  1149. typedef union WHV_X64_RDTSC_INFO {
  1150. __C89_NAMELESS struct {
  1151. UINT64 IsRdtscp : 1;
  1152. UINT64 Reserved : 63;
  1153. };
  1154. UINT64 AsUINT64;
  1155. } WHV_X64_RDTSC_INFO;
  1156. C_ASSERT(sizeof(WHV_X64_RDTSC_INFO) == 8);
  1157. typedef struct WHV_X64_RDTSC_CONTEXT {
  1158. UINT64 TscAux;
  1159. UINT64 VirtualOffset;
  1160. UINT64 Tsc;
  1161. UINT64 ReferenceTime;
  1162. WHV_X64_RDTSC_INFO RdtscInfo;
  1163. } WHV_X64_RDTSC_CONTEXT;
  1164. C_ASSERT(sizeof(WHV_X64_RDTSC_CONTEXT) == 40);
  1165. typedef struct WHV_X64_APIC_SMI_CONTEXT {
  1166. UINT64 ApicIcr;
  1167. } WHV_X64_APIC_SMI_CONTEXT;
  1168. C_ASSERT(sizeof(WHV_X64_APIC_SMI_CONTEXT) == 8);
  1169. #define WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS 6
  1170. typedef struct _WHV_HYPERCALL_CONTEXT {
  1171. UINT64 Rax;
  1172. UINT64 Rbx;
  1173. UINT64 Rcx;
  1174. UINT64 Rdx;
  1175. UINT64 R8;
  1176. UINT64 Rsi;
  1177. UINT64 Rdi;
  1178. UINT64 Reserved0;
  1179. WHV_UINT128 XmmRegisters[WHV_HYPERCALL_CONTEXT_MAX_XMM_REGISTERS];
  1180. UINT64 Reserved1[2];
  1181. } WHV_HYPERCALL_CONTEXT, *PWHV_HYPERCALL_CONTEXT;
  1182. C_ASSERT(sizeof(WHV_HYPERCALL_CONTEXT) == 176);
  1183. typedef struct WHV_X64_APIC_INIT_SIPI_CONTEXT {
  1184. UINT64 ApicIcr;
  1185. } WHV_X64_APIC_INIT_SIPI_CONTEXT;
  1186. C_ASSERT(sizeof(WHV_X64_APIC_INIT_SIPI_CONTEXT) == 8);
  1187. typedef enum WHV_X64_APIC_WRITE_TYPE {
  1188. WHvX64ApicWriteTypeLdr = 0xD0,
  1189. WHvX64ApicWriteTypeDfr = 0xE0,
  1190. WHvX64ApicWriteTypeSvr = 0xF0,
  1191. WHvX64ApicWriteTypeLint0 = 0x350,
  1192. WHvX64ApicWriteTypeLint1 = 0x360
  1193. } WHV_X64_APIC_WRITE_TYPE;
  1194. typedef struct WHV_X64_APIC_WRITE_CONTEXT {
  1195. WHV_X64_APIC_WRITE_TYPE Type;
  1196. UINT32 Reserved;
  1197. UINT64 WriteValue;
  1198. } WHV_X64_APIC_WRITE_CONTEXT;
  1199. C_ASSERT(sizeof(WHV_X64_APIC_WRITE_CONTEXT) == 16);
  1200. typedef struct WHV_RUN_VP_EXIT_CONTEXT {
  1201. WHV_RUN_VP_EXIT_REASON ExitReason;
  1202. UINT32 Reserved;
  1203. WHV_VP_EXIT_CONTEXT VpContext;
  1204. __C89_NAMELESS union {
  1205. WHV_MEMORY_ACCESS_CONTEXT MemoryAccess;
  1206. WHV_X64_IO_PORT_ACCESS_CONTEXT IoPortAccess;
  1207. WHV_X64_MSR_ACCESS_CONTEXT MsrAccess;
  1208. WHV_X64_CPUID_ACCESS_CONTEXT CpuidAccess;
  1209. WHV_VP_EXCEPTION_CONTEXT VpException;
  1210. WHV_X64_INTERRUPTION_DELIVERABLE_CONTEXT InterruptWindow;
  1211. WHV_X64_UNSUPPORTED_FEATURE_CONTEXT UnsupportedFeature;
  1212. WHV_RUN_VP_CANCELED_CONTEXT CancelReason;
  1213. WHV_X64_APIC_EOI_CONTEXT ApicEoi;
  1214. WHV_X64_RDTSC_CONTEXT ReadTsc;
  1215. WHV_X64_APIC_SMI_CONTEXT ApicSmi;
  1216. WHV_HYPERCALL_CONTEXT Hypercall;
  1217. WHV_X64_APIC_INIT_SIPI_CONTEXT ApicInitSipi;
  1218. WHV_X64_APIC_WRITE_CONTEXT ApicWrite;
  1219. WHV_SYNIC_SINT_DELIVERABLE_CONTEXT SynicSintDeliverable;
  1220. };
  1221. } WHV_RUN_VP_EXIT_CONTEXT;
  1222. C_ASSERT(sizeof(WHV_RUN_VP_EXIT_CONTEXT) == 224);
  1223. typedef enum WHV_INTERRUPT_TYPE {
  1224. WHvX64InterruptTypeFixed = 0,
  1225. WHvX64InterruptTypeLowestPriority = 1,
  1226. WHvX64InterruptTypeNmi = 4,
  1227. WHvX64InterruptTypeInit = 5,
  1228. WHvX64InterruptTypeSipi = 6,
  1229. WHvX64InterruptTypeLocalInt1 = 9
  1230. } WHV_INTERRUPT_TYPE;
  1231. typedef enum WHV_INTERRUPT_DESTINATION_MODE {
  1232. WHvX64InterruptDestinationModePhysical,
  1233. WHvX64InterruptDestinationModeLogical
  1234. } WHV_INTERRUPT_DESTINATION_MODE;
  1235. typedef enum WHV_INTERRUPT_TRIGGER_MODE {
  1236. WHvX64InterruptTriggerModeEdge,
  1237. WHvX64InterruptTriggerModeLevel
  1238. } WHV_INTERRUPT_TRIGGER_MODE;
  1239. typedef struct WHV_INTERRUPT_CONTROL {
  1240. UINT64 Type : 8;
  1241. UINT64 DestinationMode : 4;
  1242. UINT64 TriggerMode : 4;
  1243. UINT64 Reserved : 48;
  1244. UINT32 Destination;
  1245. UINT32 Vector;
  1246. } WHV_INTERRUPT_CONTROL;
  1247. C_ASSERT(sizeof(WHV_INTERRUPT_CONTROL) == 16);
  1248. typedef struct WHV_DOORBELL_MATCH_DATA {
  1249. WHV_GUEST_PHYSICAL_ADDRESS GuestAddress;
  1250. UINT64 Value;
  1251. UINT32 Length;
  1252. UINT32 MatchOnValue : 1;
  1253. UINT32 MatchOnLength : 1;
  1254. UINT32 Reserved : 30;
  1255. } WHV_DOORBELL_MATCH_DATA;
  1256. C_ASSERT(sizeof(WHV_DOORBELL_MATCH_DATA) == 24);
  1257. typedef enum WHV_PARTITION_COUNTER_SET {
  1258. WHvPartitionCounterSetMemory
  1259. } WHV_PARTITION_COUNTER_SET;
  1260. typedef struct WHV_PARTITION_MEMORY_COUNTERS {
  1261. UINT64 Mapped4KPageCount;
  1262. UINT64 Mapped2MPageCount;
  1263. UINT64 Mapped1GPageCount;
  1264. } WHV_PARTITION_MEMORY_COUNTERS;
  1265. C_ASSERT(sizeof(WHV_PARTITION_MEMORY_COUNTERS) == 24);
  1266. typedef enum WHV_PROCESSOR_COUNTER_SET {
  1267. WHvProcessorCounterSetRuntime,
  1268. WHvProcessorCounterSetIntercepts,
  1269. WHvProcessorCounterSetEvents,
  1270. WHvProcessorCounterSetApic,
  1271. WHvProcessorCounterSetSyntheticFeatures
  1272. } WHV_PROCESSOR_COUNTER_SET;
  1273. typedef struct WHV_PROCESSOR_RUNTIME_COUNTERS {
  1274. UINT64 TotalRuntime100ns;
  1275. UINT64 HypervisorRuntime100ns;
  1276. } WHV_PROCESSOR_RUNTIME_COUNTERS;
  1277. C_ASSERT(sizeof(WHV_PROCESSOR_RUNTIME_COUNTERS) == 16);
  1278. typedef struct WHV_PROCESSOR_INTERCEPT_COUNTER {
  1279. UINT64 Count;
  1280. UINT64 Time100ns;
  1281. } WHV_PROCESSOR_INTERCEPT_COUNTER;
  1282. C_ASSERT(sizeof(WHV_PROCESSOR_INTERCEPT_COUNTER) == 16);
  1283. typedef struct WHV_PROCESSOR_INTERCEPT_COUNTERS {
  1284. WHV_PROCESSOR_INTERCEPT_COUNTER PageInvalidations;
  1285. WHV_PROCESSOR_INTERCEPT_COUNTER ControlRegisterAccesses;
  1286. WHV_PROCESSOR_INTERCEPT_COUNTER IoInstructions;
  1287. WHV_PROCESSOR_INTERCEPT_COUNTER HaltInstructions;
  1288. WHV_PROCESSOR_INTERCEPT_COUNTER CpuidInstructions;
  1289. WHV_PROCESSOR_INTERCEPT_COUNTER MsrAccesses;
  1290. WHV_PROCESSOR_INTERCEPT_COUNTER OtherIntercepts;
  1291. WHV_PROCESSOR_INTERCEPT_COUNTER PendingInterrupts;
  1292. WHV_PROCESSOR_INTERCEPT_COUNTER EmulatedInstructions;
  1293. WHV_PROCESSOR_INTERCEPT_COUNTER DebugRegisterAccesses;
  1294. WHV_PROCESSOR_INTERCEPT_COUNTER PageFaultIntercepts;
  1295. WHV_PROCESSOR_INTERCEPT_COUNTER NestedPageFaultIntercepts;
  1296. WHV_PROCESSOR_INTERCEPT_COUNTER Hypercalls;
  1297. WHV_PROCESSOR_INTERCEPT_COUNTER RdpmcInstructions;
  1298. } WHV_PROCESSOR_ACTIVITY_COUNTERS;
  1299. C_ASSERT(sizeof(WHV_PROCESSOR_ACTIVITY_COUNTERS) == 224);
  1300. typedef struct WHV_PROCESSOR_EVENT_COUNTERS {
  1301. UINT64 PageFaultCount;
  1302. UINT64 ExceptionCount;
  1303. UINT64 InterruptCount;
  1304. } WHV_PROCESSOR_GUEST_EVENT_COUNTERS;
  1305. C_ASSERT(sizeof(WHV_PROCESSOR_GUEST_EVENT_COUNTERS) == 24);
  1306. typedef struct WHV_PROCESSOR_APIC_COUNTERS {
  1307. UINT64 MmioAccessCount;
  1308. UINT64 EoiAccessCount;
  1309. UINT64 TprAccessCount;
  1310. UINT64 SentIpiCount;
  1311. UINT64 SelfIpiCount;
  1312. } WHV_PROCESSOR_APIC_COUNTERS;
  1313. C_ASSERT(sizeof(WHV_PROCESSOR_APIC_COUNTERS) == 40);
  1314. typedef struct WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS {
  1315. UINT64 SyntheticInterruptsCount;
  1316. UINT64 LongSpinWaitHypercallsCount;
  1317. UINT64 OtherHypercallsCount;
  1318. UINT64 SyntheticInterruptHypercallsCount;
  1319. UINT64 VirtualInterruptHypercallsCount;
  1320. UINT64 VirtualMmuHypercallsCount;
  1321. } WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS;
  1322. C_ASSERT(sizeof(WHV_PROCESSOR_SYNTHETIC_FEATURES_COUNTERS) == 48);
  1323. typedef enum WHV_ADVISE_GPA_RANGE_CODE {
  1324. WHvAdviseGpaRangeCodePopulate = 0x00000000,
  1325. WHvAdviseGpaRangeCodePin = 0x00000001,
  1326. WHvAdviseGpaRangeCodeUnpin = 0x00000002
  1327. } WHV_ADVISE_GPA_RANGE_CODE;
  1328. typedef enum WHV_VIRTUAL_PROCESSOR_STATE_TYPE {
  1329. WHvVirtualProcessorStateTypeSynicMessagePage = 0x00000000,
  1330. WHvVirtualProcessorStateTypeSynicEventFlagPage = 0x00000001,
  1331. WHvVirtualProcessorStateTypeSynicTimerState = 0x00000002,
  1332. WHvVirtualProcessorStateTypeInterruptControllerState2 = 0x00001000,
  1333. WHvVirtualProcessorStateTypeXsaveState = 0x00001001
  1334. } WHV_VIRTUAL_PROCESSOR_STATE_TYPE;
  1335. typedef struct WHV_SYNIC_EVENT_PARAMETERS {
  1336. UINT32 VpIndex;
  1337. UINT8 TargetSint;
  1338. UINT8 Reserved;
  1339. UINT16 FlagNumber;
  1340. } WHV_SYNIC_EVENT_PARAMETERS;
  1341. C_ASSERT(sizeof(WHV_SYNIC_EVENT_PARAMETERS) == 8);
  1342. typedef enum WHV_ALLOCATE_VPCI_RESOURCE_FLAGS {
  1343. WHvAllocateVpciResourceFlagNone = 0x00000000,
  1344. WHvAllocateVpciResourceFlagAllowDirectP2P = 0x00000001
  1345. } WHV_ALLOCATE_VPCI_RESOURCE_FLAGS;
  1346. DEFINE_ENUM_FLAG_OPERATORS(WHV_ALLOCATE_VPCI_RESOURCE_FLAGS);
  1347. #define WHV_MAX_DEVICE_ID_SIZE_IN_CHARS 200
  1348. typedef struct WHV_SRIOV_RESOURCE_DESCRIPTOR {
  1349. WCHAR PnpInstanceId[WHV_MAX_DEVICE_ID_SIZE_IN_CHARS];
  1350. LUID VirtualFunctionId;
  1351. UINT16 VirtualFunctionIndex;
  1352. UINT16 Reserved;
  1353. } WHV_SRIOV_RESOURCE_DESCRIPTOR;
  1354. C_ASSERT(sizeof(WHV_SRIOV_RESOURCE_DESCRIPTOR) == 412);
  1355. typedef enum WHV_VPCI_DEVICE_NOTIFICATION_TYPE {
  1356. WHvVpciDeviceNotificationUndefined = 0,
  1357. WHvVpciDeviceNotificationMmioRemapping = 1,
  1358. WHvVpciDeviceNotificationSurpriseRemoval = 2
  1359. } WHV_VPCI_DEVICE_NOTIFICATION_TYPE;
  1360. typedef struct WHV_VPCI_DEVICE_NOTIFICATION {
  1361. WHV_VPCI_DEVICE_NOTIFICATION_TYPE NotificationType;
  1362. UINT32 Reserved1;
  1363. __C89_NAMELESS union {
  1364. UINT64 Reserved2;
  1365. };
  1366. } WHV_VPCI_DEVICE_NOTIFICATION;
  1367. C_ASSERT(sizeof(WHV_VPCI_DEVICE_NOTIFICATION) == 16);
  1368. typedef enum WHV_CREATE_VPCI_DEVICE_FLAGS {
  1369. WHvCreateVpciDeviceFlagNone = 0x00000000,
  1370. WHvCreateVpciDeviceFlagPhysicallyBacked = 0x00000001,
  1371. WHvCreateVpciDeviceFlagUseLogicalInterrupts = 0x00000002
  1372. } WHV_CREATE_VPCI_DEVICE_FLAGS;
  1373. DEFINE_ENUM_FLAG_OPERATORS(WHV_CREATE_VPCI_DEVICE_FLAGS);
  1374. typedef enum WHV_VPCI_DEVICE_PROPERTY_CODE {
  1375. WHvVpciDevicePropertyCodeUndefined = 0,
  1376. WHvVpciDevicePropertyCodeHardwareIDs = 1,
  1377. WHvVpciDevicePropertyCodeProbedBARs = 2
  1378. } WHV_VPCI_DEVICE_PROPERTY_CODE;
  1379. typedef struct WHV_VPCI_HARDWARE_IDS {
  1380. UINT16 VendorID;
  1381. UINT16 DeviceID;
  1382. UINT8 RevisionID;
  1383. UINT8 ProgIf;
  1384. UINT8 SubClass;
  1385. UINT8 BaseClass;
  1386. UINT16 SubVendorID;
  1387. UINT16 SubSystemID;
  1388. } WHV_VPCI_HARDWARE_IDS;
  1389. C_ASSERT(sizeof(WHV_VPCI_HARDWARE_IDS) == 12);
  1390. #define WHV_VPCI_TYPE0_BAR_COUNT 6
  1391. typedef struct WHV_VPCI_PROBED_BARS {
  1392. UINT32 Value[WHV_VPCI_TYPE0_BAR_COUNT];
  1393. } WHV_VPCI_PROBED_BARS;
  1394. C_ASSERT(sizeof(WHV_VPCI_PROBED_BARS) == 24);
  1395. typedef enum WHV_VPCI_MMIO_RANGE_FLAGS {
  1396. WHvVpciMmioRangeFlagReadAccess = 0x00000001,
  1397. WHvVpciMmioRangeFlagWriteAccess = 0x00000002
  1398. } WHV_VPCI_MMIO_RANGE_FLAGS;
  1399. DEFINE_ENUM_FLAG_OPERATORS(WHV_VPCI_MMIO_RANGE_FLAGS);
  1400. typedef enum WHV_VPCI_DEVICE_REGISTER_SPACE {
  1401. WHvVpciConfigSpace = -1,
  1402. WHvVpciBar0 = 0,
  1403. WHvVpciBar1 = 1,
  1404. WHvVpciBar2 = 2,
  1405. WHvVpciBar3 = 3,
  1406. WHvVpciBar4 = 4,
  1407. WHvVpciBar5 = 5
  1408. } WHV_VPCI_DEVICE_REGISTER_SPACE;
  1409. typedef struct WHV_VPCI_MMIO_MAPPING {
  1410. WHV_VPCI_DEVICE_REGISTER_SPACE Location;
  1411. WHV_VPCI_MMIO_RANGE_FLAGS Flags;
  1412. UINT64 SizeInBytes;
  1413. UINT64 OffsetInBytes;
  1414. PVOID VirtualAddress;
  1415. } WHV_VPCI_MMIO_MAPPING;
  1416. C_ASSERT(sizeof(WHV_VPCI_MMIO_MAPPING) == 32);
  1417. typedef struct WHV_VPCI_DEVICE_REGISTER {
  1418. WHV_VPCI_DEVICE_REGISTER_SPACE Location;
  1419. UINT32 SizeInBytes;
  1420. UINT64 OffsetInBytes;
  1421. } WHV_VPCI_DEVICE_REGISTER;
  1422. C_ASSERT(sizeof(WHV_VPCI_DEVICE_REGISTER) == 16);
  1423. typedef enum WHV_VPCI_INTERRUPT_TARGET_FLAGS {
  1424. WHvVpciInterruptTargetFlagNone = 0x00000000,
  1425. WHvVpciInterruptTargetFlagMulticast = 0x00000001
  1426. } WHV_VPCI_INTERRUPT_TARGET_FLAGS;
  1427. DEFINE_ENUM_FLAG_OPERATORS(WHV_VPCI_INTERRUPT_TARGET_FLAGS);
  1428. typedef struct WHV_VPCI_INTERRUPT_TARGET {
  1429. UINT32 Vector;
  1430. WHV_VPCI_INTERRUPT_TARGET_FLAGS Flags;
  1431. UINT32 ProcessorCount;
  1432. UINT32 Processors[ANYSIZE_ARRAY];
  1433. } WHV_VPCI_INTERRUPT_TARGET;
  1434. C_ASSERT(sizeof(WHV_VPCI_INTERRUPT_TARGET) == 16);
  1435. typedef enum WHV_TRIGGER_TYPE {
  1436. WHvTriggerTypeInterrupt = 0,
  1437. WHvTriggerTypeSynicEvent = 1,
  1438. WHvTriggerTypeDeviceInterrupt = 2
  1439. } WHV_TRIGGER_TYPE;
  1440. typedef struct WHV_TRIGGER_PARAMETERS {
  1441. WHV_TRIGGER_TYPE TriggerType;
  1442. UINT32 Reserved;
  1443. __C89_NAMELESS union {
  1444. WHV_INTERRUPT_CONTROL Interrupt;
  1445. WHV_SYNIC_EVENT_PARAMETERS SynicEvent;
  1446. __C89_NAMELESS struct {
  1447. UINT64 LogicalDeviceId;
  1448. UINT64 MsiAddress;
  1449. UINT32 MsiData;
  1450. UINT32 Reserved;
  1451. } DeviceInterrupt;
  1452. };
  1453. } WHV_TRIGGER_PARAMETERS;
  1454. C_ASSERT(sizeof(WHV_TRIGGER_PARAMETERS) == 32);
  1455. typedef PVOID WHV_TRIGGER_HANDLE;
  1456. typedef enum WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE {
  1457. WHvVirtualProcessorPropertyCodeNumaNode = 0x00000000
  1458. } WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE;
  1459. typedef struct WHV_VIRTUAL_PROCESSOR_PROPERTY {
  1460. WHV_VIRTUAL_PROCESSOR_PROPERTY_CODE PropertyCode;
  1461. UINT32 Reserved;
  1462. __C89_NAMELESS union {
  1463. USHORT NumaNode;
  1464. UINT64 Padding;
  1465. };
  1466. } WHV_VIRTUAL_PROCESSOR_PROPERTY;
  1467. C_ASSERT(sizeof(WHV_VIRTUAL_PROCESSOR_PROPERTY) == 16);
  1468. typedef enum WHV_NOTIFICATION_PORT_TYPE {
  1469. WHvNotificationPortTypeEvent = 2,
  1470. WHvNotificationPortTypeDoorbell = 4
  1471. } WHV_NOTIFICATION_PORT_TYPE;
  1472. typedef struct WHV_NOTIFICATION_PORT_PARAMETERS {
  1473. WHV_NOTIFICATION_PORT_TYPE NotificationPortType;
  1474. UINT32 Reserved;
  1475. __C89_NAMELESS union {
  1476. WHV_DOORBELL_MATCH_DATA Doorbell;
  1477. __C89_NAMELESS struct {
  1478. UINT32 ConnectionId;
  1479. } Event;
  1480. };
  1481. } WHV_NOTIFICATION_PORT_PARAMETERS;
  1482. C_ASSERT(sizeof(WHV_NOTIFICATION_PORT_PARAMETERS) == 32);
  1483. typedef enum WHV_NOTIFICATION_PORT_PROPERTY_CODE {
  1484. WHvNotificationPortPropertyPreferredTargetVp = 1,
  1485. WHvNotificationPortPropertyPreferredTargetDuration = 5
  1486. } WHV_NOTIFICATION_PORT_PROPERTY_CODE;
  1487. typedef UINT64 WHV_NOTIFICATION_PORT_PROPERTY;
  1488. #define WHV_ANY_VP (0xFFFFFFFF)
  1489. #define WHV_NOTIFICATION_PORT_PREFERRED_DURATION_MAX (0xFFFFFFFFFFFFFFFFULL)
  1490. typedef PVOID WHV_NOTIFICATION_PORT_HANDLE;
  1491. #define WHV_SYNIC_MESSAGE_SIZE 256
  1492. #endif /* _WINHVAPIDEFS_H_ */